The present invention broadly relates to static random access memory (SRAM) cells and deals more particularly with an SRAM cell employing a tunnel switched diode (TSD) that acts as the storage medium and is controlled by a pair of switching transistors.
Dynamic random access memories (DRAM) and static random access memories (SRAM) are being used with increasing frequency in a wide variety of applications requiring temporary data storage. The trend toward higher density and higher performance memories has resulted in a number of improvements in DRAM and SRAM architecture. For example, BJT (bipolar junction transistors) based single transistor, and diode-based single transistor SRAM cells are representative of two new memory devices. However, each of these devices has certain disadvantages. For example, BJT based SRAMs suffer from reliability problems, while diode based SRAMs are not suitable for being manufactured in CMOS processes. Conventional SRAM cells generally operate at relatively high cell current levels, but take up a relatively large area because of the need for using as many as 10 transistors per cell. Conventional DRAM cells possess a relatively small footprint since they may be formed of a single transistor and a single capacitor, however these memory devices, which rely on capacitor discharge current, are not capable of handling large cell current.
What is needed is an improved SRAM cell that is relatively small in physical area, thus allowing high memory array cell density, while also providing for relatively large cell currents that are required in high performance applications. It has been suggested that the solution may lie in the use of tunnel switched diodes (TSD), however SRAM cells utilizing TSDs have not been previously constructed into memory cell arrays as a result of their need for relatively large standby current. The present invention solves this problem by providing an SRAM cell utilizing a TSD as the storage medium, and a pair of transistors as the control devices.
According to one aspect of the invention, an SRAM cell comprises a word line, a bit line, a TSD, and a pair of electronic gate devices for controlling access to the TSD. The electronic gate devices are preferably in the form of an NMOS transistor and a PMOS transistor.
According to another aspect of the invention, an SRAM cell comprises a word line, a bit line, a bi-stable device for storing a data bit in the cell and control circuit means for controlling the state of the bi-stable device. The bi-stable device is preferably a TSD possessing a characteristic I-V curve having a region of high impedance, a region of negative differential resistance and a region of low impedance. NMOS and PMOS transistors coupled between the TSD and the word and bit lines function to access the TSD for purposes of address, read and write functions of the cell. The cells can be connected in high density, high performance arrays. The TSD""s are formed from layered materials that result in small cell size while allowing for high levels of cell current.
Accordingly, it is a primary object of the invention to provide an SRAM cell allowing relatively high levels of cell current and physically displacing a relatively small area.
Another object of the invention is to provide an SRAM cell of the type mentioned above which is well suited to be manufactured in high density arrays using conventional CMOS processing techniques.
A further object of the invention is to provide an SRAM cell as mentioned above which utilizes a minimum number of active components.
A further object of the invention is to provide an SRAM cell of the type described above which utilizes a TSD without the need for a large standby current.
These, and further objects and advantages of the invention will be made clear or will become apparent during the course of the foregoing description of a preferred embodiment of the invention.